MATRIX Resources is now “Motion Recruitment” and proud to combine job boards to bring the talent community even more expansive market opportunities.

Senior DOD Machine Learning Engineer

New, New York


Direct Hire

$150k - $200k

About the Job
Seeking AI/ML researchers passionate about developing and applying greenfield cybersecurity defenses to the hardware industry. An ideal candidate may be a software engineer with machine learning system development expertise, excellent coding skills, a background in digital logic and hardware design, and an interest and experience in applying machine learning techniques to hardware systems. Expect to become involved in developing tools for securing computer-aided design workflows, learning and applying techniques from data science and machine learning to new areas, and above all, to be a part of defending the next generation of devices. technologies to the Department of Defense and commercial customers. You will be contributing and participating in a small technical team.
Responsibilities and Duties
The best candidates will have experience:
  • Developing and implementing data science pipelines and applications
  • Understanding deep learning algorithms and their underlying mathematical foundations
  • Generating, collecting, and cleaning data
  • Working with infrastructure and acceleration for AI networks on-prem and in the cloud
  • Developing applications that implement, interface with, and support ML models
  • Understanding and implementing hardware systems and FPGAs
Minimum Qualifications
  • Ability to obtain and maintain an active US DoD secret clearance
  • B.S. or equivalent in math, engineering, or computer science
  • 4 years of experience in Python, C, and C++
  • Active interest in cybersecurity
Preferred Qualifications
  • Active secret clearance
  • Graduate degree in a related field
  • Reverse engineering experience
  • Graph neural networks
  • Experience in hardware development languages (VHDL, Verilog, etc.), workflow/toolchain (Lattice, Xilinx, etc.), and FPGA/ASIC design flows (CM, simulation, synthesis, P&R, scripting, V&V)

Posted by: Paddy Beauchamp